This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2002-126214, filed on Apr. 26, 2002, the entire contents of which are incorporated herein by reference.
The present invention relates to a peak hold circuit which detects and outputs the peak value of an input voltage.
Recently, there are growing demands for a lower supply voltage and lower power consumption for semiconductor devices that are used in various electronic devices. This necessitates that a peak hold circuit which is mounted on a semiconductor device should secure a fast and stable hold operation in addition to reduction in the supply voltage and power consumption.
FIG. 1 is a circuit diagram of a conventional peak hold circuit 50. The emitters of PNP transistors Tr1 and Tr2 are connected to a current source 1 which operates in accordance with the supply of a supply voltage Vcc. An input voltage Vin is supplied to the base of the transistor Tr1 whose collector is supplied to the collector of an NPN transistor Tr3 and the base of an NPN transistor Tr5. The emitter of the transistor Tr3 is connected to ground GND.
The collector of the transistor Tr2 is connected to the collector of an NPN transistor Tr4 and the bases of the transistors Tr3 and Tr4 and the emitter of the transistor Tr4 is connected to the ground GND. The transistors Tr3 and Tr4 form a current mirror circuit.
The base of the transistor Tr2 is connected to the collector of the transistor Tr5 and an output terminal To and the emitter of the transistor Tr5 is connected to the ground GND.
The output terminal To is connected to one end of a hold capacitor 2 whose other end is connected to the ground GND. The output terminal To is connected to a voltage supply (Vcc) via a reset switch 3.
In the peak hold circuit 50, with the supply voltage Vcc supplied, and the reset switch 3 is switched on, the hold capacitor 2 is charged and an output voltage Vout output from the output terminal To is reset to the supply voltage Vcc. As the reset switch 3 is switched on every predetermined time, the hold capacitor 2 is charged and the output voltage Vout output is reset to the supply voltage Vcc.
Next, the reset switch 3 is switched off, causing the input voltage Vin to be supplied to the base of the transistor Tr1. When the input voltage Vin is lower than the supply voltage Vcc, the collector current of the transistor Tr1 increases. As the collector currents of the transistors Tr3 and Tr4 do not increase, however, the collector current of the transistor Tr5 increases, causing the hold capacitor 2 to be discharged.
As the output voltage Vout falls and becomes equal to the input voltage Vin, the collector currents of the transistors Tr1 and Tr2 become equal to each other. As a result, the transistor Tr5 is turned off, stopping the discharging of the hold capacitor 2.
When the input voltage Vin becomes higher than the output voltage Vout, the collector current of the transistor Tr1 decreases, thereby keeping the transistor Tr5 switched off. Therefore, the output voltage Vout does not fall and the input voltage Vin is held.
The peak hold circuit 50 should improve the response speed of the output voltage Vout with respect to the input voltage Vin. This requires that a bias current IB which is supplied to the transistors Tr1 and Tr2 from the current source 1 should be increased to increase the collector currents of the transistors Tr1 and Tr2.
That is, in a case where the input voltage Vin becomes higher than the output voltage Vout after the output voltage Vout is held at the minimum voltage, the transistor Tr5 should be turned off promptly to stop the discharging of the hold capacitor 2. This requires that the base current of the transistor Tr5 should be absorbed quickly by the collector current of the transistor Tr3 which operates according to the collector current of the transistor Tr2. To improve the accuracy of the hold voltage, therefore, it is necessary to increase the bias current IB supplied from the current source 1.
If the collector current (bias current IB) of the transistor Tr2 is increased, however, the base current of the transistor Tr2 increases, so that the base current flows into the hold capacitor 2 at the time of the hold operation. This brings about the shortcoming that the output voltage Vout rises gradually, thus lowering the accuracy of the peak hold voltage.
Changing the transistors Tr1 and Tr2 to P channel MOS transistors can overcome the problem of the reduced accuracy of the hold voltage. However, the threshold value of MOS transistors is about 1 V, which is greater than the base-emitter voltage VBE of bipolar transistors. The output voltage Vout is therefore held so long as it is lower by at least 1 V than the supply voltage Vcc. The use of PMOS transistors therefore makes it difficult to cope with the reduction in supply voltage Vcc.
PMOS transistors vary considerably and the amplification factor of the PMOS transistors is smaller than that of bipolar transistors. This makes the control of the transistor Tr5 unstable, which may lead to lower accuracy of the output voltage Vout. Further, the coexistence of bipolar transistors and PMOS transistors complicates the fabrication process.
In one aspect of the present invention, a differential circuit receives first and second input voltages. The differential circuit includes a first input transistor for receiving the first voltage. A second input transistor is connected to the first input transistor to receive the second input voltage. A current source is connected to the first and second input transistors to supply bias current to the first and second input transistors. A bypass circuit is connected to the first and second input transistors and the current source, for bypassing the bias current to suppress an increase in collector current of the first input transistor or the second input transistor based on the first and second input voltages.
A further aspect of the present invention is a peak hold circuit for receiving an input voltage and making a hold voltage. The peak hold circuit includes a first input transistor having a base for receiving an input voltage. A second input transistor is connected to the first input transistor and has a base to receive the hold voltage. A current mirror circuit is connected to the first and second input transistors to supply identical collector current to the first and second input transistors. A hold capacitor is connected to the second input transistor to supply the hold voltage to the second input transistor. A reset switch is connected to the hold capacitor to reset the hold voltage. A hold-voltage setting transistor is connected to the hold capacitor and the first and second input transistors to receive base current from the collector of the first input transistor and make the hold voltage coincide with the input voltage in accordance with the base current. A bypass circuit is connected to the second input transistor, for bypassing bias current to be supplied to the second input transistor when the hold-voltage setting transistor is turned off.
A further aspect of the present invention is a peak hold circuit for receiving an input voltage and making a hold voltage. The peak hold circuit includes a first differential circuit including a first input transistor having a base for receiving the input voltage and a collector, a second input transistor connected to the first input transistor and having a base for receiving the hold voltage, and a first current mirror circuit, connected to the first and second input transistors, for supplying a same collector current to the first and second input transistors. A hold capacitor is connected to the second input transistor to supply the hold voltage to the second input transistor. A reset switch is connected to the hold capacitor to reset the hold voltage. A hold-voltage setting transistor is connected to the hold capacitor and the first and second input transistors to receive base current from the collector of the first input transistor and make the hold voltage coincide with the input voltage in accordance with the base current. A second differential circuit is connected in parallel to the first differential circuit and includes a third input transistor having a base for receiving the input voltage, a fourth input transistor connected to the hold capacitor and having a base for receiving the hold voltage, and a second current mirror circuit, connected to the third and fourth input transistors, for supplying identical collector current to the third and fourth input transistors. A negative feedback circuit is connected to the second input transistor, for reducing a bias current to the second input transistor in accordance with the hold voltage when the hold-voltage setting transistor is turned off due to voltage difference between the input voltage and the hold voltage.
A further aspect of the present invention is a method of holding a voltage in a peak hold circuit that includes a current source, a bypass circuit connected to the current source, a first input transistor, a second input transistor, a hold capacitor connected to the second input transistor for holding the voltage, and a hold-voltage setting transistor connected to the hold capacitor for charging and discharging the hold capacitor. The method includes steps of supplying bias current from the current source to the first input transistor and the second input transistor, supplying an input voltage to the first input transistor and supplying a hold voltage from the hold capacitor to the second input transistor, allowing the first input transistor to enable the hold-voltage setting transistor to discharge the hold capacitor when the input voltage is lower than the hold voltage, and disabling the hold-voltage setting transistor and allowing the bypass circuit to bypass bias current to be supplied to the second input transistor, when the hold voltage decreases to the input voltage.
A further aspect of the present invention is a comparator for receiving first and second input voltages. The comparator includes a first input transistor for receiving the first input voltage. A second input transistor is connected to the first input transistor to receive the second input voltage. A current mirror circuit is connected to the first and second input transistors to supply identical collector current to the first and second input transistors. A negative feedback circuit is connected to the first and second input transistors to suppress an increase in collector current of the first input transistor or the second input transistor based on the first and second input voltages. An output transistor is connected to the current mirror circuit and the negative feedback circuit and is driven by the current mirror circuit and the negative feedback circuit.
A further aspect of the present invention is a comparator for receiving first and second input voltages. The comparator includes a first input transistor having a base for receiving the first input voltage and a collector. A second input transistor having an emitter connected to an emitter of the first input transistor and a base to receive the second input voltage. The comparator includes high-potential and low-potential voltage supplies. A current source is connected between the emitter of the first input transistor, the emitter of the second input transistor and the high-potential voltage supply. A first NPN transistor has a collector connected to the collector of the first input transistor, an emitter connected to a low-potential voltage supply, and a base. A second NPN transistor has a base connected to the base and the collector of the first NPN transistor and an emitter connected to the low-potential voltage supply. A feedback transistor has a collector connected to the current source, the emitter of the first input transistor and the emitter of the second input transistor, a base connected to the collector of the first input transistor and an emitter connected to the low-potential voltage supply. A drive transistor has a base connected to the base of the feedback transistor and an emitter connected to the low-potential voltage supply. An output transistor has a base connected to a collector of the drive transistor, an emitter connected to the high-potential voltage supply and a collector. An output terminal is connected to the collector of the output transistor.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.